Informatics Publishing Limited

V. Soumya ¹, Raghavendra Shirodkar ², A. Prathiba ¹, V. S. Kanchana Bhaaskaran ¹

Affiliations
1 School of Electronics Engineering, VIT University Chennai Campus, Chennai-600127, Tamil Nadu, IN
2 NXP Semiconductors India PVT LTD, Bangalore-560045, Karnataka, IN

Abstract

Background: With the advent in hand held mobile computing devices, the demand for high performance compact processors is increasing. In this work a processor is designed with hardwired instructions for elementary mathematical functions like sine, cosine, sinh, cosh, division and multiplication. Methods: The processor employs Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of the above mentioned instructions. The parallel and pipelined implementation of the processor is carried out. The pipelined processor is configured as waveform generator. The novelty of this work is the integration of both trigonometric and hyperbolic operations in the same processor. Findings: ASIC Implementation is carried out with 40nm technology libraries. The parallel processor so designed operates at maximum frequency of 24.23 MHz and pipelined processor operates at maximum frequency of 261.36 MHz. Conclusion: This increase in operating frequency is achieved at the cost of increased silicon area and optimal power dissipation. The waveform generator generates sine, cosine waves of 3.5 MHz and sine hyperbolic, cosine hyperbolic waves and exponential waves of 7.9 MHz. The limitation being the waveform generator generates waves of constant frequency. Additional circuit is required in generating waves of different frequencies.

Keywords

Coordinate Rotation Digital Computer (CORDIC), Parallel Architecture, Pipelined Architecture, Waveform Generator

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A. Prathiba ¹, V. S. Kanchana Bhaaskaran ¹

Affiliations
1 School of Electronics Engineering, VIT University Chennai, Chennai - 600127, IN

Abstract

Objective: This paper presents the Field Programmable Gate Array (FPGA) implementations of the different block cipher mode architectures of the ISO standardized light weight block cipher PRESENT, designed for resource constrained devices. Methods/ Statistical Analysis: The performance evaluations compare the implementations of the different block cipher modes, namely Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback Mode (CFB), Output Feed Back Mode (OFB) and CounTeR (CTR) mode for the PRESENT cipher. The throughput of encryption of three successive 64 bit blocks of data ranges from 565.312Mbps to 574.784Mbps for the modes other than the cipher feedback mode in the Spartan-3 FPGA. The throughput for providing confidentiality through encryption in the cipher feedback mode arrives as 68.912 Mbps, 155.392Mbps and 300.8 Mbps for a 64 bit block of data for the input streams of size 8 bits, 16 bits and 32 bits respectively. Findings: The throughput of the block cipher mode hardware architectures of the light weight cipher PRESENT demonstrates the high speed performance of the cipher in encryption/decryption of data as blocks and streams. Application/ Improvement: The significance of the proposed work is to know the hardware performance of the different modes of operation for the light weight block cipher PRESENT. The performance estimation of the block cipher modes operations of the PRESENT cipher definition in hardware have been carried out for the first time.

Keywords

Block Cipher Modes, FPGA, Internet of Things (IoT), Light Weight Cipher.

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Savio Victor Gomes ¹, P. Sasipriya ¹, V. S. Kanchana Bhaaskaran ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai - 600 127, Tamil Nadu, IN

Abstract

Background: Multiplication forms one of the most power hungry operations in a digital system. It is used extensively in the digital signal processing applications and in any general purpose processors. Hence, the efficient hardware realization of the multiplier is crucial in ensuring that the processors operate within the power limits and without getting overheated. Method: In order to make the multipliers more power efficient, ways have been found to curtail the spurious glitching in the internal nodes of the multiplier. Latch adder with the delay lines is used in the multiplier to equalize the delay of the partial products. Findings: In this paper, a novel 24 transistor Latch Adder (LA) is proposed. It is validated using the Wallace tree multiplier as a bench marking circuit. Wallace tree multiplier is implemented using the proposed latch adder and delay lines in the internal nodes. Comparison is made with the multipliers constructed using various full adder configurations available in the literature. Conclusion: It is proved that the proposed multiplier circuit achieves the power reduction of 20% compared to the multiplier using 16T full adder. The multiplier is simulated using the industry standard Cadence® Virtuoso tool in 180nm technology library files and the simulation results confirm the low power operation of the multiplier.

Keywords

Latch Based Adder, Low Power Adder, Low Power Multiplier, Wallace Tree Multiplier

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K. Vishnuvardhan Rao ¹, A. Anita Angeline ², V. S. Kanchana Bhaaskaran ¹

Affiliations
1 School of Electronics Engineering Department, VIT University Chennai, 632014, Tamil Nadu, IN
2 School of Electronics Engineering Department, VIT University Chennai, 632014, Tamil Nadu

Abstract

Objectives: This paper presents the design of a 16 bit Reduced Instruction Set Computing (RISC) processor using the custom design approach. Statistical Analysis: The type of processor employed in a system claims its efficiency. The compressed instruction incorporated in the design reduces the area and power dissipation of the processor. Findings: Various functional blocks of the processor such as the Control Unit, Instruction Decoder, Instruction Register unit and Arithmetic and Logical Unit (ALU) are designed using the Cadence® Virtuoso tool and the simulations are carried out using Cadence® ADE_L Tool using 180nm technology library from TSMC. The integration of the various functional bocks is done based on the finite states arrived at, for the execution of each instruction. Conclusion: The RISC processor is found to consume 68.9mW of power for the execution of the AND instruction with a delay of 1600ns. It consumes 77.6mW of power dissipation for the execution of the ADD instruction with a delay of 1900ns.

Keywords

Data Driven Dynamic Logic (D3L), Domino Logic, Introduction, Low Power ALU, RISC Processor Custom Design

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Ramdas Bhanudas Khaladkar ¹, A. Anita Angeline ¹, V. S. Kanchana Bhaaskaran ¹

Affiliations
1 School of Electronics Engineering Department, VIT University, Chennai Campus, Chennai-600127, Tamil Nadu, IN

Abstract

Background: The dynamic gates produce an extremely high power overhead due to their high switching activity if used in designing a compact and high speed circuit. This paper presents a dynamic logic basedarithmetic and logical unit that can realize reduced switching power to alleviate such a problem. Methods: This is achieved by employingthe modified dual VT domino logic and Limited Switch Dynamic Logic (LSDL) mechanisms. The LSDL technique provides a static like switching action which exhibits lesser area requirement and high speed performance. Findings: The design of the arithmetic and logical units using the conventional dynamic logic, modified dual VT domino logic and the limited switch dynamic logic are presented in the paper for validating the claim. Conclusion: Thesimulation results depict the fact that the use of the LSDL shows 52.86%reduction in the dynamic power in comparison with the conventional dynamic logic. The circuits are implemented using Cadence® Virtuoso tools and 45nm technology node library files. The power analyses are performed using Cadence® Virtuoso Spectre tool.

Keywords

ALU Design, Dynamic Circuits, Limited Switch Dynamic Logic (LSDL), Low Power

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